A fabricated semiconductor die often contains tens of millions of electrical components, e.g., transistors, capacitors and resistors, etc. Before shipment to a customer, manufacturers ordinarily test the die to make sure that its electrical components function appropriately. If the die fails any test, its test result is usually the starting point of electrical failure analysis (EFA) whose goal is to locate manufacturing defects on the die surface using, e.g., a scanning electron microscope (SEM). Frequently, the electrical test result of an IC only suggests an electrical failure existing at a certain portion of the logical circuit and offers little guidance with respect to the exact physical location of a manufacturing defect on the die that causes the electrical failure. Therefore, there is a need for translating information about an electrical failure derived from an electrical test result into a set of (x, y) coordinates on the die surface so that the region defined by the coordinates can be further examined to determine if it includes any manufacturing detects responsible for the failure.